Semiconductor Engineering

DFT For SoCs Is Last, First, And Everywhere In Between

Back in the dawn of time, IC test was the last task in the design flow. First, you designed the chip and then you wrote the functional test program to verify it performed as expected after ...
Semiconductor Engineering

How To Manage DFT For AI Chips

Semiconductor companies are racing to develop AI-specific chips to meet the rapidly growing compute requirements for artificial intelligence (AI) systems. AI chips from companies like Graphcore and ...
Electronic Design

DFT Strategies for SOC Designs

Many IC designers finally have embraced design for testability (DFT) in the form of scan insertion for digital circuit designs because of the significant time-to-production advantages these techniques ...
EDN

Boost DFT efficiency for large SoCs

One significant design challenge for today’s SoCs is managing the impact of the very large design size on EDA tools and flows. Front-end and back-end design flows have managed this challenge by ...
Electronic Design

What’s Next for Physically Aware DFT?

Why isolated flows negatively impact design schedule and PPA. Benefits of unified DFT, synthesis, and physical design flows. Physical implementation optimization methods for test compression and scan ...