As the Semiconductor industry is growing so does the density of devices on chip. With the increasing density and decreasing spacing rules, the most significant effect that takes birth is parasitic.

In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize ...

TSMC’s roadmap announcement for their 28 nm node yesterday has stirred considerable controversy already. The issue is the company’s decision to divide their process development into two tracks: one to ...

Ferroelectric FETs and memories are beginning to show promise as researchers begin developing and testing next-generation transistors. One measure of the efficiency of a transistor is the subthreshold ...