Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Groundbreaking benefits of using artificial intelligence in design verification. How SHAPley values can help engineers optimize debugging in design verification. Achieving low-latency SoC ...

Chip designs are optimized for lower cost, better performance, or lower power. The same cannot be said about verification, where today very little effort is spent on reducing execution cost, run time, ...

Challenges facing chip design verification engineers are plentiful, but the opportunities, especially for AI applications, are abundant Challenges facing chip design verification engineers are ...

Evolving Verification Environments It was standard practice in the early days of hardware design to design a chip and then verify it. However this methodology started to break down in the 1980s when ...

The limitations of traditional SPICE simulations. Role of production-grade AI in transforming EDA. Applications of AI in day-to-day engineering. The future of AI in analog design. In the realm of ...

In partnership with the Israel Tech Challenge, Apple is co-hosting an event at its Israel headquarters to discuss a new Design Verification Engineering course. This course will be a ten month-long ...

The rise of 5G and satellite connectivity is creating new roles in the semiconductor industry. Engineering students with an ...

When it comes to verification and validation, medical device companies need to ensure that what they're doing actually makes sense. Known colloquially as "V&V," for many it feels like you're on the ...

People freely interchange the terms “test” and “verification.” It’s understandable when terms like testcase, testbench and device under test (DUT) are in conjunction with different types of ...