This application note discusses phase frequency detector characteristics that affect phase-locked loop (PLL) dead band and jitter performance. In PLLs that employ charge pump loop filter designs the ...

This is Part 2 of a three-part series. As discussed in Part 1 and recapped here, modern wireless communications systems (mainly superheterodyne radio transceivers) are now required to deliver higher ...

Clock signals provide reference timing to every integrated circuit and electrical system. While consumer applications typically use simple quartz crystals for reference-clock generation, other ...

An important task for a digital communications receiver is to remove any frequency/phase offsets that might exist between the transmitter and receiver oscillators. Designers typically implement a ...

Phase-locked-loop (PLL) frequency synthesizers are signal sources often employed in many types of electronic equipment. They show up as clock sources in high-frequency instruments and as local ...

One of the most challenging tasks in analog circuit design is to adapt a functional block to ever new CMOS process technology. For digital circuits the number of gates per square mm approx. doubles ...

I have always had a soft spot for phase-locked loops – at least, I have since I first found out what they were. What I like about them is that they servo into the best answer for a given situation – ...

Related to my search for reduced motor noise (and thanks to all who have made suggestions – ‘scope avaunt this weekend), is a search for speed stability in that motor*. And to someone who is in love ...