EDN

Equivalency checking verifies sequential changes

Systems on chip (SoC) and processor design teams are challenged to meet aggressive power, performance and area requirements. As chip complexity grows, teams must verify thousands of lines of code to ...
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...
Design-Reuse

Sequential equivalence checking for RTL models

In this paper, we examine the need for formal sequential equivalence checking across pairs of RTL models. We present scenarios that call for modifying the sequential behavior of RTL models while ...
Semiconductor Engineering

Verifying Power Optimized Designs Using Sequential Analysis

All power optimization tools can perform combinational optimization, where there is an opportunity to gate a register clock input, based on the combinational logic that is feeding the register’s data ...
Design-Reuse

Averant Adds RTL and Gate Level Combinational Equivalency Checker

HAYWARD, Calif.--August 01, 2011--Averant Inc., the First In Formalâ„¢ leader in property verification of RTL designs for digital circuits, today announces the release of Solidify 5.4. Some of the ...
Semiconductor Engineering

Power Reduction Through Sequential Optimization

Dealing with power is a multifaceted challenge and is an equal-opportunity problem — everybody can contribute to the solution and at many levels of abstraction. At the architectural or system level, ...
Electronic Design

Sequential Power Optimization Tool Pinpoints Clock-Gating Opportunities At RTL

Unlike combinational power reduction tools, PowerPro CG identifies and generates sequential clock-gating transformations. It fits into existing design flows with industry-standard library, timing, and ...
EDN

Sequential equivalence checking for RTL models

In this paper, we examine the need for formal sequential equivalence checkingacross pairs of RTL models. We present scenarios that call for modifying thesequential behavior of RTL models while ...