In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize ...

TSMC’s roadmap announcement for their 28 nm node yesterday has stirred considerable controversy already. The issue is the company’s decision to divide their process development into two tracks: one to ...

Energy saving: artist’s impression of the gate material with negative capacitance. (Courtesy: Ella Maru Studio) By exploiting a curious effect called negative capacitance, researchers have designed a ...

The electron transport properties of graphene devices are critical to many applications, but our understanding of these properties is still incomplete, in spite of rapid advances in recent years. One ...

It has been long known that complementary metal-oxide semiconductor (CMOS) transistors suffer from a scaling issue. As CMOS field-effect transistors (FETs) get smaller, they become less power ...

If you are going to use a silicon carbide (SiC) MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) in your next development, you will ask yourself: how do I develop the best gate driver for it ...