IEEE

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency

Abstract: Large Language Models (LLMs) have demonstrated promising capabilities in generating Verilog code from module specifications. To improve the quality of such generated Verilog codes, previous ...
IEEE

LLM4Verilog: Building Large-Scale, High-Quality Data Infrastructure for Verilog Code Generation via Community Efforts

Abstract: Despite recent advancements in code generation with large language models (LLMs), generating hardware code such as Verilog remains a significant challenge due to the scarcity of large-scale, ...
GitHub

amba_ahb_m2s3.v

AMBA bus lecture material. Contribute to adki/AMBA_AXI_AHB_APB development by creating an account on GitHub.